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HT82B60R i/o mcu with usb interface rev. 1.10 1 february 1, 2011 general description the HT82B60R is a high performance, risc architec- ture microcontroller device specifically designed for multiple i/o control product applications. the advantages of low power consumption, i/o flexibil- ity, timer functions, integrated usb interface, serial in- terfaces, lcd drive capability, power down and wake-up functions, watchdog timer etc, make the de- vice extremely suitable for use in computer peripheral product applications as well as many other applications such as industrial control, consumer products, subsys - tem controllers, etc. these wide range of functions, together with a fully inte- grated 6mhz or 12mhz oscillator, ensure that products can be implemented with a minimum of external compo- nents and smaller circuit board areas, providing users with the benefits of lower overall product costs. features operating voltage: f sys =6m/12mhz: 3.3v~5.5v low voltage reset function 42 bidirectional i/o lines (max.) 8-bit programmable timer/event counter with overflow interrupt 16-bit programmable timer/event counter and overflow interrupts watchdog timer ps2 and usb modes supported usb 2.0 low speed function 4 endpoints supported -- endpoint 0 included 8192 16 program memory 216 8 data memory ram integrated 1.5k resistor between v33o and usbpdn pins for usb applications fully integrated 6mhz or 12mhz oscillator all i/o pins have wake-up functions power-down function and wake-up feature reduce power consumption serial interface module -- i 2 c and spi functions 4 com lines for lcd display driving external interrupt pin 8-level subroutine nesting up to 0.33 s instruction cycle with 12mhz system clock at v dd =5v bit manipulation instruction 15-bit table read instruction 63 powerful instructions all instructions in one or two machine cycles 20/28/48-pin ssop, 32-pin qfn and 48-pin lqfp packages
block diagram pin assignment HT82B60R rev. 1.10 2 february 1, 2011

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pin description pin name i/o options description pa0~pa5 pa6/tmr0 pa7/tmr1 i/o pull-high wake-up nmos/cmos/pmos bidirectional 8-bit input/output port. each pin can be configured as a wake-up input by a configuration option. software instructions de - termine if the pin is a cmos output or nmos, pmos or schmitt trigger input. configuration options determine if the structures are cmos, nmos or pmos types. configuration options determine if the pins have pull-high resistors. tmr0 and tmr1 are pin-shared with pa6 and pa7, respectively. pb0/sdi/sda pb1/sdo pb2/sck/scl pb3/scs pb4/pck pb5/int pb6~pb7 i/o pull-high wake-up bidirectional 8-bit input/output port. each nibble can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. con - figuration options determine if the pins have pull-high resistors. the power supply for i/o pins pb0~pb7 can be selected to be vdd or v33o using a configuration option. pins pb0~pb3 are pin-shared with the serial interface pins. pin pb4 is pin-shared with the periph - eral clock output and pb5 is shared with the external interrupt pin. pc0/com0 pc1/com1 pc2/com2 pc3/com3 pc4~pc7 i/o pull-high wake-up bidirectional 8-bit input/output port. each nibble can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. con - figuration options determine if the pins have pull-high resistors. pc0~pc3 are pin-shared with com0~com3 pd0~pd7 i/o pull-high wake-up bi-directional 8-bit input/output port. each nibble can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. con - figuration options determine if the pins have pull-high resistors. pe0~pe7 i/o pull-high wake-up bidirectional 8-bit input/output port. each nibble can be configured as a wake-up input by a configuration option. software instructions determine if the pin is a cmos output or schmitt trigger input. con- figuration options determine if the pins have pull-high resistors. pf0, pf1 i/o pull-high wake-up bidirectional 2-bit input/output port. each pin can be configured as a wake-up input by a configuration option. software instructions de- termine if the pin is a cmos output or schmitt trigger input. config- uration options determine if the pins have pull-high resistors. usbpdp/clk i/o usbpdp line. usb function is controlled by software control regis- ters. usbpdn/data i/o usbpdn line. usb function is controlled by software control regis - ters. res i schmitt trigger reset input. active low gnd digital negative power supply, ground vdd digital positive power supply v33o o 3.3v regulator output note: as the pin description table applies to the largest package size not all pin may exist on smaller packages. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT82B60R rev. 1.10 3 february 1, 2011
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage (integrated oscillator) f sys =6mhz or 12mhz 3.3 5.5 v i dd operating current 5v no load, f sys =6mhz 6.5 12 ma no load, f sys =12mhz 7.5 16 ma i stb1 standby current 5v no load, system halt, usb mode, usr.5=1 usr.4=0, lvr disable, wdt disable, clr d_sr [scc.2], clr usbcken [scc.3], clr bgoff [scc.4], set clk_adj [scc.7] 400 a i stb2 standby current 5v no load, system halt, ps2 mode, usr.5=0 usr.4=1, lvr disable, wdt disable, clr d_sr [scc.2], clr usbcken [scc.3], set bgoff [scc.4], set clk_adj [scc.7] 10 a v il input low voltage for pa, pc, pd, pe, pf0~pf1 5v where v ddio =v dd or v33o by option for pb 0 0.8 v input low voltage for pb 0 0.3v ddio v input low voltage for res pin 0 0.4v dd v v ih input high voltage for pa, pc, pd, pe, pf0~pf1 5v where v ddio =v dd or v33o by option for pb 2 5v input high voltage for pb 0.8v ddio v ddio v input high voltage for res pin 0.9v dd v dd v v lvr low voltage reset 5v 2.0 2.6 3.2 v v v33o 3.3v regulator output for usb sie 5v i v33o =70ma 3.0 3.3 3.6 v i ol output sink current for i/o port 5v v ol =0.4v 24 ma i oh output source current for i/o port 5v v oh =3.4v 2 4 ma i lcd_bias vdd/2 bias current for lcd 5v lcdc. rsel[1:0]=00 17.5 25 32.5 a lcdc. rsel[1:0]=01 35 50 65 a lcdc. rsel[1:0]=10 70 100 130 a lcdc. rsel[1:0]=11 140 200 260 a v com vdd/2 voltage for lcd com port 5v no load 0.475 0.500 0.525 v dd r ph pull-high resistance for clk, data 5v 4.7 k pull-high resistance for pa, pb, pc, pd, pe and pf0~pf1 20 50 70 k HT82B60R rev. 1.10 4 february 1, 2011
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f rcsys rc clock with 8-bit prescaler register 5v 14 32 48 khz t wdt watchdog time-out period (system clock) 1024 1/f rcsys t usb usbpdp, usbpdn rising & falling time 75 300 ns t ost oscillation start-up timer period 1024 t sys t oscsetup crystal setup 5 ms f ino125v internal oscillator frequency for 12mhz 4.0v~ 5.5v 10.80 12.00 13.20 mhz f ino123v internal oscillator frequency for 12mhz 3.0~ 4.0v 10.56 12.00 13.44 mhz f inousb internal oscillator frequency with usb mode 4.2~ 5.5v 11.82 12.00 12.18 mhz note: t sys =1/f sys power_on period = t wdt +t ost +t oscsetup wdt time_out in normal mode = 1/ f rcsys 256 wdts + t wdt wdt time_out in power down mode = 1/ f rcsys 256 wdts + t ost +t oscsetup trimmed for 5v operation using factory trim values. frequency trim to 12mhz
3% HT82B60R rev. 1.10 5 february 1, 2011
HT82B60R rev. 1.10 6 february 1, 2011 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to the inter - nal system architecture. the range of devices take ad - vantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all operations of the instruction set. it car - ries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the inter - nal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional i/o and a/d control sys - tem with maximum reliability and flexibility. clocking and pipelining the system clock is derived from an internal oscillator and is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cy - cles, the pipelining structure of the microcontroller en - sures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. an extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non-consecutive program memory address. it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. + ! < = > : ? ! < = $ > + ! < = @ $ > : ? ! < = > + ! < = @ % > : ? ! < = @ $ > @ $ @ % a =
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HT82B60R rev. 1.10 7 february 1, 2011 when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis - carded and a dummy cycle takes its place while the cor - rect instruction is obtained. the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short pro - gram jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 loca - tions. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessi - ble under program control. manipulating the pcl might cause program branching, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, sp, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the con- tents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, sig - naled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine in - struction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. arithmetic and logic unit alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic op- erations of the instruction set. connected to the main microcontroller data bus, the alu receives related in- struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. as these alu calculation or oper- ations may result in carry, borrow or other status changes, the status register will be correspondingly up- dated to reflect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa mode program counter bits *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000000000000 usb interrupt 0000000000100 timer/event counter 0 overflow 0000000001000 timer/event counter 1 overflow 0000000001100 spi/i 2 c interrupt 0000000010000 external interrupt 0000000010100 skip program counter + 2 loading pcl *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *12~*0: program counter bits @7~@0: pcl bits #12~#0: instruction code bits s12~s0: stack register bits ! a ( 0 $ a ( 0 % a ( 0 / a ( 0
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HT82B60R rev. 1.10 8 february 1, 2011 logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti program memory the program memory is the location where the user code or program is stored. this is a one-time programmable, otp, memory type device where users can program their application code into the device. by using the appropriate programming tools, otp devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. otp devices are also applicable for use in applications that require low or medium volume production runs. structure the program memory has a capacity of 8k by 16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by separate table pointer registers. special vectors within the program memory, certain locations are re- served for special usage such as reset and interrupts. location 000h this area is reserved for program initialization. after chip reset, the program always begins execution at lo- cation 000h. location 004h this area is reserved for the usb interrupt service program. if the usb interrupt is activated, the interrupt is enabled and the stack is not full, the program jumps to this location and begins execution. location 008h this area is reserved for the timer/event counter 0 in - terrupt service program. if a timer interrupt results from a timer/event counter 0 overflow, and if the in - terrupt is enabled and the stack is not full, the program jumps to this location and begins execution. location 00ch this area is reserved for the timer/event counter 1 in - terrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, and the inter - rupt is enabled and the stack is not full, the program jumps to this location and begins execution. location 010h this internal vector is used by the spi/i 2 c interrupt. when either an spi or i 2 c bus, dependent upon which one is selected, requires data transfer, the program will jump to this location and begin execution if the spi/i 2 c interrupt is enabled and the stack is not full. location 014h this vector is used by the external interrupt. if the ex - ternal interrupt pin receives an active edge, the pro - gram will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. $ + + + & $ # . ! " * ! " * 2 2 6 & 2 $ 2 & 2 $ 6 & ! ! * 2 2 2 & : ? ! ! " * : 0 ! 2 ! ! " * 2 2 & 2 2 & : 0 ! $ ! ! " * % program memory structure instruction table location bits b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrdc [m] pc12 pc11 pc10 pc9 pc8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m]11111@7@6@5@4@3@2@1@0 table location note: pc12~pc8: current program counter bits @7~@0: table pointer tblp bits tbhp register bit 4~bit 0 when tbhp is enabled.
HT82B60R rev. 1.10 9 february 1, 2011 table location any location in the program memory can be used as look-up tables. there are three methods to read the program memory data using two table read instruc - tions: tabrdc and tabrdl , transfer the con - tents of the lower-order byte to the specified data memory, and the higher-order byte to tblh. the three methods are shown as follows: using the instruction tabrdc [m] for the current program memory page, where one page= 256words, where the table location is defined by tblp in the current page. this is where the config - uration option has disabled the tbhp register. using the instruction tabrdc [m] , where the ta - ble location is defined by registers tblp and tbhp. here the configuration option has enabled the tbhp register. using the instruction tabrdl [m] , where the ta - ble location is defined by registers tblp in the last page which has the address range 1f00h~ 1ffffh. only the destination of the lower-order byte in the ta - ble is well-defined, the other bits of the table word are transferred to the lower portion of tblh, and the re - maining 1-bit words are read as 0 . the table higher-order byte register (tblh) is read only. the ta - ble pointers, tblp and tbhp, are read/write regis- ters, which indicate the table location. before accessing the the table, the locations must be placed in the tblp and tbhp registers (if the configuration option has disabled tbhp then the value in tbhp has no effect). tblh is read only and cannot be restored. if the main routine and the isr (interrupt service rou- tine) both employ the table read instruction, the con- tents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr and errors can occur. using the table read instruction in the main routine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt should be disabled prior to the table read in - struction. it will not be enabled until the tblh has been backed up. all table related instructions require two cycles to complete the operation. these areas may function as normal program memory depending on the requirements. once tbhp is enabled, the instruction tabrdc [m] reads the program memory data as defined by the tblp and tbhp values. if the program memory code option has disabled tbhp, the instruction tabrdc [m] reads the program memory data as defined by tblp only in the current program memory page. look-up table any location within the program memory can be defined as a look-up table where programmers can store fixed data. to use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the tblp register and the higher order address in the tbhp register. these two registers define the full address of the look-up table. using the tbhp must be selected by configuration op - tion, if not used table data can still be accessed but only the lower byte address in the current page or last page can be defined. after setting up the table pointers, the table data can be retrieved from the current program memory page or last program memory page using the tabrdc[m] or tabrdl [m] instructions, respectively. when these in - structions are executed, the lower order table byte from the program memory will be transferred to the user de - fined data memory register [m] as specified in the in - struction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as 0 . table program example the following example shows how the table pointer and table data is defined and retrieved from the microcontroller. this example uses raw table data lo- cated in the last page which is stored there using the org statement. the value at this org statement is 1f00h which refers to the start address of the last page within the 8k program memory of device. the ta - ble pointer is setup here to have an initial value of 06h . this will ensure that the first data read from the data ta - ble will be at the program memory address 1f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first ad - dress of the present page if the tabrdc [m] instruc - tion is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrdl [m] in - struction is executed.
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HT82B60R rev. 1.10 10 february 1, 2011 tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise table pointer - note that this address is referenced mov tblp,a ; to the last page or present page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer to tempregl ; data at prog. memory address 1f06h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer to tempreg2 ; data at prog.memory address 1f05h transferred to tempreg2 and tblh ; in this example the data 1ah is transferred to ; tempreg1 and data 0fh to register tempreg2 ; the value 00h will be transferred to the high byte register tblh : : org 1f00h ; sets initial address of last page dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use the table read instructions. if using the table read instructions, the interrupt service routines may change the value of tblh and subsequently cause er- rors if used again by the main routine. as a rule it is rec- ommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the inter- rupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary in - formation is stored. divided into two sections, the first of these is an area of ram where special function registers are located. these registers have fixed locations and are necessary for correct operation of the device. many of these registers can be read from and written to di - rectly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. structure the two sections of data memory, the special purpose and general purpose data memory are located at con - secutive locations. all are implemented in ram and are 8 bits wide. the start address of the data memory for all devices is the address 00h . registers which are com - mon to all microcontrollers, such as acc, pcl, etc., have the same data memory address. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. it is this area of ram memory that is known as general purpose data memory. this area of data memory is fully accessible by the user pro- gram for both read and write operations. by using the set [m].i and clr [m].i instructions, individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the data memory. 2 2 & % & + + & % 4 & " "
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data memory structure note: most of the data memory bits can be directly manipulated using the set [m].i and clr [m].i with the exception of a few dedicated bits. the data memory can also be accessed through the memory pointer register mp.
HT82B60R rev. 1.10 11 february 1, 2011 special purpose data memory this area of data memory is where registers, necessary for the correct operation of the microcontroller, are stored. it is divided into two banks, bank 0 and bank1. most of the registers are both readable and writeable but some are protected and are readable only, the de - tails of which are located under the relevant special function register section. note that for locations that are unused, any read instruction to these addresses will return the value 00h . the special purpose registers for the usb interface are stored in bank 1 which can only be accessed by first setting the bank pointer to a value of 01h and then us - ing indirect addressing register iar1 and memory pointer mp1. bank 1 can only be accessed indirectly us - ing the mp1 memory pointer, direct addressing is not possible. special function registers to ensure successful operation of the microcontroller, certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control. the location of these registers within the data memory be - gins at the address 00h. any unused data memory lo - cations between these special function registers and the point where the general purpose memory begins is re - served and attempting to read data from these locations will return a value of 00h. indirect addressing register iar0, iar1 the indirect addressing registers, iar0 and iar1, al - though having their locations in normal ram register space, do not actually physically exist as normal regis - ters. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory ad - dressing, where the actual memory address is speci - fied. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corre - sponding memory pointer, mp0 or mp1. acting as a pair, iar0 and mp0 can together only access data from bank 0, while the iar1 and mp1 register pair can ac- cess data from both bank 0 and bank 1. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indi- rectly will result in no operation. memory pointer mp0, mp1 for all devices, two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers pro - viding a convenient way with which to address and track data. when any operation to the relevant indirect ad - dressing registers is carried out, the actual address that the microcontroller is directed to, is the address speci - fied by the related memory pointer. mp0 can only ac - cess data in bank 0 while mp1 can access both banks. 2 2 & 2 $ & 2 % & 2 / & 2 6 & 2 5 & 2 # & 2 4 & 2 & 2 3 & 2 8 & 2 . & 2 & 2 & 2 : & 2 + & $ 2 & $ $ & $ % & $ / & $ 6 & $ 5 & $ # & $ 4 & $ & $ 3 & $ 8 & $ . & $ & $ & $ : & $ + & % 2 & % $ & % % & % / & % 6 & % 5 & % # & % 4 & c ! g 2 g 8 2 2 8 $ $ . 8 ( . ( . ( & 8 7 2 2 2 $ & $ ( $ 8 8 . . : : + + 7 $ . & ( ( 2 ( $ 8 ( % 6 2 & 6 $ & 6 % & 6 / & 6 6 & 6 5 & 6 # & 6 4 & 6 & 6 3 & 6 8 & 6 . & . h 8 : h ( 8 8 ( ( : : : 7 h : 7 + + 2 + + $ + + % + + / special purpose data memory
HT82B60R rev. 1.10 12 february 1, 2011 data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with first ram address mov mp0,a ; setup memory pointer with first ram address loop: clr iar0 ; clear the data at address defined by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specific data memory ad - dresses. accumulator acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register pcl to provide additional program control functions, the low byte of the program counter is made accessible to pro - grammers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily imple - mented. loading a value directly into this pcl register will cause a jump to the specified program memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current program memory page are per - mitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers tblp, tblh, tbhp these two special function registers are used to control operation of the look-up table which is stored in the pro - gram memory. tblp and tbhp are the table pointers and indicate the location where the table data is located. their value must be setup before any table read commands are executed. their values can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. watchdog timer register wdts the watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect program memory addresses. to implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. to provide variable watchdog timer reset times, the watchdog timer clock source can be divided by various division ra- tios, the value of which is set using the wdts register. by writing directly to this register, the appropriate divi- sion ratio for the watchdog timer clock source can be setup. note that only the lower 3 bits are used to set divi - sion ratios between 1 and 128. status register status this 8-bit register contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). these arithmetic/logical operation and system manage - ment flags are used to record the status and operation of the microcontroller. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, opera - tions related to the status register may give different re - sults due to the different instruction operations. the to flag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt in - struction. the pdf flag is affected only by executing the halt or clr wdt instruction or during a system power-up.
HT82B60R rev. 1.10 13 february 1, 2011 the z, ov, ac and c flags generally reflect the status of the latest operations. c is set if an operation results in a carry during an ad - dition operation or if a borrow does not take place dur - ing a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib - ble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the high- est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the interrupt rou - tine can change the status register, precautions must be taken to correctly save it. interrupt control registers intc0, intc1 the microcontrollers provide two internal timer/event counter overflow interrupts, one usb interrupt, a com - bined spi/i 2 c interrupt and an external pin interrupt. by setting various bits within these registers using standard bit manipulation instructions, the enable/disable func - tion of each interrupt can be independently controlled. a master interrupt bit within this register, the emi bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. this bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the reti instruction. timer/event counter registers tmr0, tmr0c, tmr1h, tmr1l, tmr1c both devices possess a single internal 8-bit count-up timer. an associated register known as tmr0 is the lo - cation where the timers 8-bit value is located. this regis - ter can also be preloaded with fixed data to allow different time intervals to be setup. an associated con - trol register, known as tmr0c, contains the setup infor - mation for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function. all devices possess one internal 16-bit count-up timer. an associated register pair known as tmr1l/tmr1h is the location where the timer 16-bit value is located. this register can also be preloaded with fixed data to allow different time intervals to be setup. an associated con- trol register, known as tmr1c, contains the setup infor- mation for this timer, which determines in what mode the timer is to be used as well as containing the timer on/off control function. input/output ports and control registers within the area of special function registers, the i/o registers and and their associated control registers play a prominent role. all i/o ports have a designated regis - ter correspondingly labeled as pa, pb, pc, pd, pe and pf0~pf1. these labeled i/o registers are mapped to specific addresses within the data memory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. with each i/o port there is an associated control register labeled pac, pbc, pcc, pdc, pec and pfc, also mapped to specific addresses with the data memory. the control register specifies which pins of that port are set as inputs and which are set as outputs. to setup a pin as an input, the corresponding bit of the control reg - ister must be set high, for an output it must be set low. during program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the i/o ports. one flexible feature of these regis - ters is the ability to directly program single bits using the + * i 8
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HT82B60R rev. 1.10 14 february 1, 2011 set [m].i and clr [m].i instructions. the ability to change i/o pins from output to input and vice versa by manipulating specific bits of the i/o control registers dur - ing normal program operation is a useful feature of these devices. bank pointer bp the special purpose data memory is divided into two banks, bank 0 and bank 1. the usb control registers are located in bank 1, while all other registers are lo - cated in bank 1. the bank pointer selects which bank data is to be accessed from. if bank 0 is to be accessed then bp must be set to a value of 00h, while if bank 1 is to be accessed then bp must be set to a value of 01h. serial interface registers the device contains two serial interfaces, an spi and an i 2 c interface. the simctl0, simctl1, simctl2 and simar are the control registers for the serial interface function while the simdr is the data register for the se- rial interface data. software com register scomc the pins pc0~pc3 on port c can be used as com lines to drive an external lcd panel. to implement this func- tion, the lcdc register is used to setup the correct bias voltages on these pins. input/output ports holtek microcontrollers offer considerable flexibility on their i/o ports. with the input or output designation of ev - ery pin fully under user program control, pull-high op - tions for all ports and wake-up options on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. depending upon which package is chosen, the microcontroller provides up to 42 bidirectional input/out - put lines labeled with port names pa, pb, pc, pd, pe and pf0~pf1. these i/o ports are mapped to the data memory with addresses as shown in the special purpose data mem - ory table. for input operation, these ports are non-latch - ing, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m] , where m de - notes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter - nal resistor. to eliminate the need for these external re - sistors, i/o pins, when configured as an input have the capability of being connected to an internal pull-high re - sistor. the pull-high resistors are selectable via configu - ration options and are implemented using weak pmos transistors. a pin or nibble option on the i/o ports can be selected to select pull-high resistors. port a cmos/nmos/pmos structure the pins on port a can be setup via configuration option to be either cmos, nmos or pmos types. port b vdd/v33o option structure the power supply for the port b pins can be setup via configuration option to be either vdd or v33o. port pin wake-up if the halt instruction is executed, the device will enter the power down mode, where the system clock will stop resulting in power being conserved, a feature that is im - portant for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port pins from high to low. after a halt instruction forces the microcontroller into entering the power down mode, the processor will remain in a low-power state un- til the logic condition of the selected wake-up pin on the port pin changes from high to low. this function is espe- cially suitable for applications that can be woken up via external switches. each pin on pa, pb, pc, pd, pe and pf0~pf1 has the capability to wake-up the device on an external falling edge. note that some pins can only be setup nibble wide whereas other can be bit selected to have a wake-up function. i/o port control registers each i/o port has its own control register pac, pbc, pcc, pdc, pec and pfc, to control the input/output configuration. with this control register, each cmos out - put or input with or without pull-high resistor structures can be reconfigured dynamically under software control. each of the i/o ports is directly mapped to a bit in its asso - ciated port control register. note that several pins can be setup to have nmos outputs using configuration options. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1 . this will then allow the logic state of the input pin to be di - rectly read by instructions. when the corresponding bit of the control register is written as a 0 , the i/o pin will be setup as an output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program
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HT82B60R rev. 1.10 15 february 1, 2011 will in fact only read the status of the output data latch and not the actual logic status of the output pin. pin-shared functions the flexibility of the microcontroller range is greatly en - hanced by the use of pins that have more than one func - tion. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over - come. for some pins, the chosen function of the multi-function i/o pins is set by configuration options while for others the function is set by application pro - gram control. external interrupt input the external interrupt pin, int is pin-shared with the i/o pin pb5. for applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal i/o pin, however to do this, the external interrupt enable bit in the intc1 register must be disabled. external timer0 clock input the external timer pin tmr0 is pin-shared with the i/o pin pa6. to configure this pin to operate as timer input, the corresponding control bits in the timer control reg - ister must be correctly set. for applications that do not require an external timer input, this pin can be used as a normal i/o pin. note that if used as a normal i/o pin the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation. external timer1 clock input the external timer pin tmr1 is pin-shared with the i/o pin pa7. to configure this pin to operate as timer input, the corresponding control bits in the timer control reg- ister must be correctly set. for applications that do not require an external timer input, this pin can be used as a normal i/o pin. note that if used as a normal i/o pin the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation. external interrupt input the external interrupt pin int is pin-shared with the i/o pin pb5. for applications not requiring an external inter - rupt input, the pin-shared external interrupt pin can be used as a normal i/o pin, however to do this, the exter - nal interrupt enable bits in the intc1 register must be disabled. com driver pins pins pc0~pc3 on port c can be used as lcd com driver pins. this function is controlled using the lcdc register which will generate the necessary 1/2 bias sig - nals on these four pins. serial interface module the device pins, pb0~pb3, are pin-shared with pins sda, scl, scs, sck, sdi, sdo. the choice of which function is used is selected using the simctl0 register. i/o pin structures the diagram illustrates a generic i/o pin internal struc - tures. as the exact logical construction of the i/o pin will differ and as the pin-shared structures are not illustrated this diagram is supplied as a guide only to assist with the functional understanding of the i/o pins. programming considerations within the user program, one of the first things to con- sider is port initialisation. after a reset, all of the data and port control register will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. if the pac, pbc, * * / / = . > ; a " " !
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HT82B60R rev. 1.10 16 february 1, 2011 pcc, pdc, pec and pfc port control register, are then programmed to setup some pins as outputs, these out - put pins will have an initial high output value unless the associated pa, pb, pc, pd, pe and pf port data regis - ters are first programmed. selecting which pins are in - puts and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control reg - ister using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must first read in the data on the entire port, modify it to the required new bit values and then re - write this data back to the output ports. all pins have the additional capability of providing wake-up functions. when the device is in the power down mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port pins. single or multiple pins can be setup to have this function. timer/event counters the provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. this device contains two count-up timers of 8-bit and 16-bit capacities respec- tively. as each timer has three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. there are two types of registers related to the timer/event counters. the first is the register that con - tains the actual value of the timer/event counter and into which an initial value can be preloaded, and is known as tmr0, tmr1h or tmr1l. reading from this register retrieves the contents of the timer/event coun - ter. the second type of associated register is the timer control register, which defines the timer options and determines how the timer/event counter is to be used, and has the name tmr0c or tmr1c. this device can have the timer clocks configured to come from the inter - nal clock sources. in addition, the timer clock source can also be configured to come from the external timer pins. the external clock source is used when the timer/event counter is in the event counting mode, the clock source being provided on the external timer pin. the pin has the name tmr0 or tmr1 and is pin-shared with an i/o pin. depending upon the condition of the t0e or t1e bit in the timer control register, each high to low, or low to high transition on the external timer input pin will incre - ment the timer/event counter by one. configuring the timer/event counter input clock source the timer/event counter s clock can originate from var - ious sources. the system clock source is used when the timer/event counter 0 is in the timer mode or in the pulse width measurement mode. the instruction clock source (system clock source divided by 4) is used when the timer/event counter 1 is in the timer mode or in the pulse width measurement mode. the external clock source is used when the timer/event counter is in the event counting mode, the clock source being provided on the external timer pin, tmr0 or tmr1. depending upon the condition of the t0e or t1e bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. timer register tmr0, tmr1l/tmr1h the timer registers are special function registers located in the special purpose ram data memory and are the places where the actual timer values are stored. for 8-bit timer/event counter 0, this register is known as tmr0. for 16-bit timer/event counter 1, the timer reg- isters are known as tmr1l and tmr1h. the value in the timer registers increases by one each time an inter- nal clock pulse is received or an external transition oc- curs on the external timer pin. the timer will count from the initial value loaded by the preload register to the full count of ffh for the 8-bit timer or ffffh for the 16-bit timer at which point the timer overflows and an internal interrupt signal is generated. the timer value will then be reset with the initial preload register value and con - tinue counting. to achieve a maximum full range count of ffh for the 8-bit timer or ffffh for the 16-bit timer, the preload reg - isters must first be cleared to all zeros. it should be noted that after power-on, the preload register will be in an unknown condition. note that if the timer/event counter is switched off and data is written to its preload registers, this data will be immediately written into the actual timer registers. however, if the timer/event counter is enabled and counting, any new data written into the preload data registers during this period will re - main in the preload registers and will only be written into the timer registers the next time an overflow occurs. for the 16-bit timer/event counter which has both low byte and high byte timer registers, accessing these reg - isters is carried out in a specific way. it must be note when using instructions to preload data into the low byte timer register, namely tmr1l, the data will only be placed in a low byte buffer and not directly into the low byte timer register. the actual transfer of the data into $ % / 6 $ % / 6 1
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HT82B60R rev. 1.10 17 february 1, 2011 4 2 7 2 2 2 $ 2 ) *
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! $ $ 2 2 $ $ $ 2 2 $ 2 $ $ : 7 " ! d g 2 g : 0 ! ! $ 0 $ c ! ! 1 ! 2 c ! ! ! : 0 ! ! $ ! ! ! $ c ! 2 c 7 " ! d g 2 g " ! ! 0 0 ! ! " ) ! timer/event counter 1 control register
HT82B60R rev. 1.10 18 february 1, 2011 the low byte timer register is only carried out when a write to its associated high byte timer register, namely tmr1h, is executed. on the other hand, using instruc - tions to preload data into the high byte timer register will result in the data being directly written to the high byte timer register. at the same time the data in the low byte buffer will be transferred into its associated low byte timer register. for this reason, the low byte timer regis - ter should be written first when preloading data into the 16-bit timer registers. it must also be noted that to read the contents of the low byte timer register, a read to the high byte timer register must be executed first to latch the contents of the low byte timer register into its associ - ated low byte buffer. after this has been done, the low byte timer register can be read in the normal way. note that reading the low byte timer register will result in read - ing the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register. timer control register tmr0c/tmr1c the flexible features of the holtek microcontroller timer/event counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. for de - vices are two timer control registers known as tmr0c, tmr1c . it is the timer control register together with its corresponding timer registers that control the full opera- tion of the timer/event counters. before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization. to choose which of the three modes the timer is to oper- ate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the timer control register, which are known as the bit pair t0m1/t0m0 or t1m1/t1m0 respectively, depend - ing upon which timer is used, must be set to the required logic levels. the timer-on bit, which is bit 4 of the timer control register and known as t0on or t1on, depend - ing upon which timer is used, provides the basic on/off control of the respective timer. setting the bit high allows the counter to run, clearing the bit stops the counter. if the timer is in the event count or pulse width measure - ment mode, the active transition edge level type is se - lected by the logic level of bit 3 of the timer control register which is known as t0e or t1e, depending upon which timer is used. configuring the timer mode in this mode, the timer/event counter can be utilised to measure fixed time intervals, providing an internal inter - rupt signal each time the timer/event counter over - flows. to operate in this mode, the operating mode select bit pair, t0m1/t0m0 or t1m1/t1m0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the timer mode bit7 bit6 10 in this mode the internal clock, f sys /4 is used as the inter - nal clock for the timer/event counters. after the other bits in the timer control register have been setup, the enable bit t0on or t1on, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run.each time an internal clock cycle occurs, the timer/event counter increments by one. when it is full and overflows, an interrupt signal is generated and the timer/event counter will reload the value already loaded into the preload register and con- tinue counting. the interrupt can be disabled by ensur- ing that the timer/event counter interrupt enable bit in the interrupt control register, intc0, is reset to zero. configuring the event counter mode in this mode, a number of externally changing logic events, occurring on the external timer pin, can be re - corded by the timer/event counter. to operate in this mode, the operating mode select bit pair, t0m1/t0m0 or t1m1/t1m0, in the timer control register must be set to the correct value as shown. control register operating mode select bits for the event counter mode bit7 bit6 01 ! ! ! " @ $ @ % @ 7 @ 7 @ $ timer mode timing chart @ % : ? ! : 0 ! ! ! ! @ / @ $ event counter mode timing chart
HT82B60R rev. 1.10 19 february 1, 2011 in this mode, the external timer pin, tmr0 or tmr1, is used as the timer/event counter clock source, however it is not divided by the internal prescaler. after the other bits in the timer control register have been setup, the enable bit t0on or t1on, which is bit 4 of the timer control register, can be set high to enable the timer/event counter to run. if the active edge select bit t0e or t1e, which is bit 3 of the timer control register, is low, the timer/event counter will increment each time the external timer pin receives a low to high transition. if the active edge select bit is high, the counter will incre - ment each time the external timer pin receives a high to low transition. when it is full and overflows, an interrupt signal is generated and the timer/event counter will re - load the value already loaded into the preload register and continue counting. the interrupt can be disabled by ensuring that the timer/event counter interrupt enable bit in the interrupt control register, intc0, is reset to zero. as the external timer pin is shared with an i/o pin, to en - sure that the pin is configured to operate as an event counter input pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. it should be noted that in the event counting mode, even if the microcontroller is in the power down mode, the timer/event counter will continue to record externally changing logic events on the timer input pin. as a result when the timer overflows it will generate a timer interrupt and corresponding wake-up source. configuring the pulse width measurement mode in this mode, the timer/event counter can be utilised to measure the width of external pulses applied to the ex - ternal timer pin. to operate in this mode, the operating mode select bit pair, t0m1/t0m0 or t1m1/t1m0, in the timer control register must be set to the correct valueas shown. control register operating mode select bits for the pulse width measurement mode bit7 bit6 11 in this mode the internal clock, f sys /4 is used as the inter - nal clock for the timer/event counters. after the other bits in the timer control register have been setup, the enable bit t0on or t1on, which is bit 4 of the timer control register, can be set high to enable the timer/event counter, however it will not actually start counting until an active edge is received on the external timer pin. if the active edge select bit t0e or t1e, which is bit 3 of the timer control register, is low, once a high to low transition has been received on the external timer pin, tmr0 or tmr1, the timer/event counter will start counting until the external timer pin returns to its original high level. at this point the enable bit will be automati - cally reset to zero and the timer/event counter will stop counting. if the active edge select bit is high, the timer/event counter will begin counting once a low to high transition has been received on the external timer pin and stop counting when the external timer pin re - turns to its original low level. as before, the enable bit will be automatically reset to zero and the timer/event counter will stop counting. it is important to note that in the pulse width measurement mode, the enable bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the enable bit can only be reset to zero under program control. the residual value in the timer/event counter, which can now be read by the program, therefore represents the length of the pulse received on the external timer pin. as the enable bit has now been reset, any further transitions on the external timer pin will be ignored. not until the enable bit is again set high by the program can the timer begin further pulse width measurements. in this way, single shot pulse measurements can be easily made. it should be noted that in this mode the timer/event counter is controlled by logical transitions on the exter - nal timer pin and not by the logic level. when the timer/event counter is full and overflows, an interrupt signal is generated and the timer/event counter will re - load the value already loaded into the preload register and continue counting. the interrupt can be disabled by @ $ @ % @ / @ 6 : ? ! ! ! " 2 7 $ 7 = ) 2 : $ : k 2 > " ! ! ! " " 0
1 ! 1 $ < pulse width measure mode timing chart
HT82B60R rev. 1.10 20 february 1, 2011 ensuring that the timer/event counter interrupt enable bit in the interrupt control register, intc0, is reset to zero. as the external timer pin is shared with an i/o pin, to en - sure that the pin is configured to operate as a pulse width measurement pin, two things have to happen. the first is to ensure that the operating mode select bits in the timer control register place the timer/event coun - ter in the pulse width measurement mode, the second is to ensure that the port control register configures the pin as an input.ot by the logic level. i/o interfacing the timer/event counter, when configured to run in the event counter or pulse width measurement mode, re - quire the use of the external tmr0 and tmr1 pins for correct operation. as these pins are shared pins they must be configured correctly to ensure they are setup for use as timer/event counter inputs and not as a nor - mal i/o pins. this is implemented by ensuring that the mode select bits in the timer/event counter control reg - ister, select either the event counter or pulse width mea - surement mode. additionally the port control register bits for these pins must be set high to ensure that the pin is setup as an input. any pull-high resistor configuration option on these pins will remain valid even if the pin is used as a timer/event counter input. programming considerations when configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. in this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respec - tive internal interrupt vector. for the pulse width mea - surement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. as this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. as a result, there may be small differences in measured values requiring programmers to take this into account during programming. the same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. when the timer/event counter is read, or if data is writ - ten to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. care must be taken to ensure that the timers are prop - erly initialised before using them for the first time. the associated timer enable bits in the interrupt control reg - ister must be properly set otherwise the internal interrupt associated with the timer will remain inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. it is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. after the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control regis - ter. note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. when the timer/event counter overflows, its corre - sponding interrupt request flag in the interrupt control register will be set. if the timer interrupt is enabled this will in turn generate an interrupt signal. however irre - spective of whether the interrupts are enabled or not, a timer/event counter overflow will also generate a wake-up signal if the device is in a power-down condi- tion. this situation may occur if the timer/event counter is in the event counting mode and if the external signal continues to change state. in such a case, the timer/event counter will continue to count these exter- nal events and if an overflow occurs the device will be woken up from its power-down condition. to prevent such a wake-up from occurring, the timer interrupt re- quest flag should first be set high before issuing the halt instruction to enter the power down mode. timer program example this program example shows how the timer/event counter registers are setup, along with how the inter - rupts are enabled and managed. note how the timer/event counter is turned on, by setting bit 4 of the timer control register. the timer/event counter can be turned off in a similar way by clearing the same bit. this example program sets the timer/event counter to be in the timer mode, which uses the internal system clock as the clock source.
HT82B60R rev. 1.10 21 february 1, 2011 org 04h ; usb interrupt vector reti org 08h ; timer/event counter interrupt vector jmp tmr0int ; jump here when timer0 overflows : org 20h ; main program ;internal timer/event counter 0 interrupt routine tmr0int: : ; timer/event counter 0 main program placed here : reti : : begin: ;setup timer registers mov a,09bh ; setup timer preload value mov tmr0,a; mov a,080h ; setup timer control register mov tmr0c,a ; timer mode ; setup interrupt register mov a,005h ; enable master interrupt and timer interrupt intc0,a set tmr0c.4 ; start timer/event counter - note mode bits must be previously setup interrupts interrupts are an important part of any microcontroller system. when an internal function such as a timer/event counter overflow or a usb interrupt occur or an external event or spi/i 2 c interrupt occur , their cor- responding interrupt will enforce a temporary suspen- sion of the main program allowing the microcontroller to direct attention to their respective needs. the external interrupt is controlled by the action of the external inter- rupt pin, while the internal interrupts are controlled by the timer/event counter overflow, usb interrupt or re- ception. interrupt register overall interrupt control, which means interrupt enabling and request flag setting, is controlled by two interrupt control registers. by controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. the global enable flag if cleared to zero will disable all interrupts. interrupt operation when an interrupt occurs, if their appropriate interrupt enable bit is set, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp statement which will jump to another section of program which is known as the interrupt ser- vice routine. here is located the code to control the ap- propriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and al- lows the microcontroller to continue with normal execu- tion at the point where the interrupt occurred. the various interrupt enable bits, together with their as - sociated request flags, are shown in the accompanying diagram with their order of priority. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked, as the emi bit will be cleared au - tomatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests oc - cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re - corded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the rou - tine, to allow interrupt nesting. if the stack is full, the in - terrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full.
HT82B60R rev. 1.10 22 february 1, 2011 8

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: 0 ! ! 2 0 1 ) ! " , + 2 + : 2 : 0 ! ! $ 0 1 ) ! " , + $ + : $ : ! " , + + ( ) : ? ! ! " , + : + : : % interrupt structure interrupt priority interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in case of simultaneous requests, the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector usb interrupt 1 0004h timer/event counter 0 overflow interrupt 2 0008h timer/event counter 1 overflow interrupt 3 000ch spi/i 2 c interrupt 4 0010h external interrupt 5 0014h in cases where both external and internal interrupts are enabled and where an external and internal interrupt oc - curs simultaneously, the external interrupt will always have priority and will therefore be serviced first. suitable masking of the individual interrupts using the interrupt registers can prevent simultaneous occurrences. usb interrupt the usb interrupts are triggered by the following usb events causing the related interrupt request flag, usbf, to be set. access of the corresponding usb fifo from pc a usb suspend signal from the pc a usb resume signal from the pc a usb reset signal when the interrupt is enabled, the stack is not full and the usb interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag, usbf, and the emi bit will be cleared to disable other interrupts. when the pc host accesses the fifo of the device, the corresponding request bit, usr, is set, and a usb inter - rupt is triggered. so the user can easy determine which fifo has been accessed. when the interrupt has been served, the corresponding bit should be cleared by firm- ware. when the device receive a usb suspend signal from host pc, the suspend line (bit0 of usc) is set and a usb interrupt is also triggered. also when device receive a resume signal from host pc, the resume line (bit3 of usc) is set and a usb inter- rupt is triggered. timer/event counter interrupt for a timer/event counter interrupt to occur, the global interrupt enable bit, emi, and the corresponding timer interrupt enable bit, et0i/et1i, must first be set. an ac - tual timer/event counter interrupt will take place when the timer/event counter interrupt request flag, t0f/t1f, is set, a situation that will occur when the timer/event counter overflows. when the interrupt is enabled, the stack is not full and a timer/event counter overflow occurs, a subroutine call to the timer interrupt vector at location 08h/0ch, will take place. when the in - terrupt is serviced, the timer interrupt request flag, t0f/t1f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts.
HT82B60R rev. 1.10 23 february 1, 2011 + *
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HT82B60R rev. 1.10 24 february 1, 2011 spi/i 2 c interface interrupt for an spi/i 2 c interrupt to occur, the global interrupt en - able bit, emi, and the corresponding interrupt enable bit, simi must be first set. an actual spi/i 2 c interrupt will take place when the spi/i 2 c interrupt request flag, simf, is set, a situation that will occur when a byte of data has been transmitted or received by the spi/i 2 c interface or when an i 2 c address match occurs. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the spi/i 2 c interface or an i 2 c address match occurs, a subroutine call to the spi/i 2 c interrupt vector, will take place. when the inter - rupt is serviced, the spi/i 2 c request flag, simf, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. external interrupt for an external interrupt to occur, the global interrupt en - able bit, emi, and external interrupt enable bit, eei, must first be set. an actual external interrupt will take place when the external interrupt request flag, eif, is set, a situation that will occur when a negative edge transition appears on the int pin. the external interrupt pin is pin-shared with the i/o pin pb5 and can only be configured as an external interrupt pin if its correspond - ing external interrupt enable bit in the intc1 register has been set. the pin must also be setup as an input by setting the corresponding pbc.5 bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the exter- nal interrupt pin, a subroutine call to the external inter- rupt vector will take place. when the interrupt is serviced, the external interrupt request flags, eif, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on this pin will remain valid even if the pin is used as an external interrupt input. programming considerations by disabling the interrupt enable bits, a requested inter - rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt control register until the corre - sponding interrupt is serviced or until the request flag is cleared by a software instruction. it is recommended that programs do not use the call subroutine instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well con - trolled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only the program counter is pushed onto the stack. if the contents of the accumulator or status register are al - tered by the interrupt service program, which may cor - rupt the desired control sequence, then the contents should be saved in advance. reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is first applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, af - ter a short delay, will be in a well defined state and ready to execute the first program instruction. after this power-on reset, certain important internal registers will be set to defined states before the program com - mences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. one example of this is where after power has been applied and the microcontroller is already running, the res line is force- fully pulled low. in such a case, known as a normal oper- ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the microcontroller. all types of re- set operations result in different register conditions be- ing setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is imple - mented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. as well as ensuring that the program memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. although the microcontroller has an internal rc reset function, if the vdd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing a
HT82B60R rev. 1.10 25 february 1, 2011 proper reset operation. in such cases it is recom - mended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the figures stands for system start-up timer. for most applications a resistor connected between vdd and the res pin and a capacitor connected be - tween vss and the res pin will provide a suitable ex - ternal reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset cir - cuit shown is recommended. more information regarding external reset circuits is located in application note ha0075e on the holtek website. res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by external hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initi - ated from this point. note that as the external reset pin is also pin-shared with pa7, if it is to be used as a reset pin, the correct reset configuration option must be se - lected. low voltage reset lvr the microcontroller contains a low voltage reset cir - cuit in order to monitor the supply voltage of the de - vice. the lvr function is selected via a configuration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. for a valid lvr signal, a low sup - ply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that spec - ified by t lvr in the a.c. characteristics. if the low sup - ply voltage state does not exceed this value, the lvr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be se - lected via configuration options. watchdog time-out reset during normal operation the watchdog time-out reset during normal opera- tion is the same as a hardware res pin reset except that the watchdog time-out flag to will be set to 1 . watchdog time-out reset during power down the watchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the pro - gram counter and the stack pointer will be cleared to 0 and the to flag will be set to 1 . refer to the a.c. characteristics for t sst details. : * ! ! 2 < 3 * power-on reset timing chart : * * 2 < $ + $ 2 2 a basic reset circuit : 2 < $ + $ 2 2 a * * 2 < 2 $ + $ 2 a enhanced reset circuit : ! ! 2 < 3 * 2 < 6 * res reset timing chart ( * ! ! low voltage reset timing chart wdt time-out reset during power down timing chart ! ! wdt time-out reset during normal operation timing chart
HT82B60R rev. 1.10 26 february 1, 2011 reset initial conditions the different types of reset described affect the reset flags in different ways. these flags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the power down function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 res reset during power-on 0 0 res wake-up during power down 0 0 res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: u stands for unchanged the following table indicates the way in which the vari - ous components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off prescaler the timer counter prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects the microcontroller in - ternal registers. register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000h 0000h 0000h 0000h 0000h 0000h 0000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 1000 0111 1000 0111 1000 0111 1000 0111 uuuu uuuu 1000 0111 1000 0111 status --00 xxxx --1u uuuu --00 uuuu --00 uuuu --11 uuuu --uu uuuu --01 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu -000 0000 -000 0000 intc1 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu --00 --00 --00 --00 tmr0 xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu 00-0 1000 00-0 1000 tmr1h xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu tmr1l xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- uu-u u--- uu-u u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111
HT82B60R rev. 1.10 27 february 1, 2011 register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* usb reset (normal) usb reset (halt) pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pe 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pec 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu 1111 1111 1111 1111 pf ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu ---- --11 ---- --11 pfc ---- --11 ---- --11 ---- --11 ---- --11 ---- --uu ---- --11 ---- --11 tbhp ---x xxxx ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu usc 11xx 0000 11xx xu0x 11xx 0000 11xx 0000 uuxx xuux uu00 0u00 uu00 0u00 scc 0000 0000 uuu0 uuu0 0000 0000 0000 0000 uuuu uuxu 0uu0 u000 0uu0 u000 usr 0000 0000 u0uu 0000 0000 0000 0000 0000 u0uu 0000 u1uu 0000 u1uu 0000 usb_stat --xx 0000 --xx 0000 --xx 0000 --xx 0000 --xx 0000 --xx 0000 --xx 0000 pipe_ctrl 0000 1110 uuuu uuuu 0000 1110 0000 1110 uuuu uuuu 0000 1110 0000 1110 awr 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 pipe 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 stall 0000 1110 uuuu uuuu 0000 1110 0000 1110 uuuu uuuu 0000 1110 0000 1110 sies 0x0x x000 uuuu uuuu 0x0x x000 0x0x x000 uuuu uuuu 0x0x x000 0x0x x000 misc 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 endpt_en 0000 0111 uuuu uuuu 0000 0111 0000 0111 uuuu uuuu 0000 0111 0000 0111 fifo0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 fifo3 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 simctl0 1110 0000 1110 0000 1110 0000 1110 0000 uuuu uuu0 1110 0000 1110 0000 simctl1 1000 0001 1000 0001 1000 0001 1000 0001 xxxu uxux 1000 0001 1000 0001 simdr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu xxxx xxxx xxxx xxxx simar/ simctl2 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 lcdc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu note: * means warm reset - not implemented u means unchanged x means unknown
HT82B60R rev. 1.10 28 february 1, 2011 oscillator the clock source for these devices is provided by an in - tegrated oscillator requiring no external components. this oscillator has two fixed frequencies of either 6mhz, or 12mhz, the selection of which is made by the sysclk bit in the scc register. watchdog timer oscillator the wdt oscillator is a fully self-contained free running on-chip rc oscillator with a typical period of 65 sat5v requiring no external components. when the device en - ters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. however, to preserve power in certain applications the wdt oscillator can be disabled via a configuration option. power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode. when the device enters this mode, the normal operating current, will be reduced to an ex - tremely low standby current level. this occurs because when the device enters the power down mode, the sys - tem oscillator is stopped which reduces the power con- sumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. this feature is extremely important in applica- tion areas where the microcontroller must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the halt instruc - tion in the application program. when this instruction is executed, the following will occur: the system oscillator will stop running and the appli - cation program will stop at the halt instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt or rtc oscillator. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down flag, pdf, will be set and the watchdog time-out flag, to, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the microcontroller to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit de - signer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be con - nected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or con - nected only to external circuits that do not draw current, such as other cmos inputs. if the configuration options have enabled the watchdog timer internal oscillator then this will continue to run when in the power down mode and will thus consume some power. for power sensitive applications it may be therefore preferable to use the system clock source for the watchdog timer. if any i/o pins are configured as a/d analog inputs using the channel configuration bits in the adcr register, then the a/d converter will be turned on and a certain amount of power will be consumed. it may be therefore desirable before entering te power down mode to ensure that the a/d converter is powered down by ensuring that any a/d input pins are setup as normal logic inputs with pull-high resistors. wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: an external reset an external all i/o ports a system interrupt a wdt overflow if the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a wdt overflow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam - ining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the halt instruction. the to flag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other flags remain in their original status.
HT82B60R rev. 1.10 29 february 1, 2011 each pin on all i/o ports can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. when a i/o ports pin wake-up occurs, the program will resume execution at the instruction following the halt instruction. if the system is woken up by an interrupt, then two possi - ble situations may occur. the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe - cution at the instruction following the halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set to 1 be - fore entering the power down mode, the wake-up func - tion of the related interrupt will be disabled. no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal sys - tem operation resumes. however, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the halt instruction, this will be executed immediately after the 1024 system clock period delay has ended. watchdog timer the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (sys - tem clock divided by 4), enabled using a configuration option. this timer is designed to prevent a software mal - function or sequence jumping to an unknown location with unpredictable results. if the watchdog timer is dis - abled, all the executions related to the wdt results in no operation. once the internal wdt oscillator (rc oscillator normally with a period of 78 s) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approxi - mately 20ms. this time-out period may vary with tem - perature, vdd and process variations. by using the wdt prescaler, longer time-out periods can be realized. writing data to ws2, ws1, ws0 (bit 2, 1, 0 of the wdts) can give different time-out periods. if wdts2, wdts1, wdts0 are all equal to 1 , the division ratio is up to 1:128, and the maximum time-out period is 2.6s. if the wdt oscillator is disabled, the wdt clock source may still come from the instruction clock and operate in the same manner except that in the power down mode state the wdt may stop counting and lose its protecting purpose. in this situation the wdt logic can be restarted by external logic. the high nibble and bit 3 of the wdts are reserved for user defined flags, which can be used to indicate some specified status. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom- mended, since the halt will stop the system clock. ! = % 5 # > 4 $ ; 2 m % a
" ! 1 ! " ! ( $ + ( % + $ % ! ! ( ( 1 b 6 a ! 1 ! " ! watchdog timer
HT82B60R rev. 1.10 30 february 1, 2011 bit no. label function 0 1 2 wdts0 wdts1 wdts2 watchdog timer division ratio selection bits bit 2,1,0 = 000, division ratio = 1:1 bit 2,1,0 = 001, division ratio = 1:2 bit 2,1,0 = 010, division ratio = 1:4 bit 2,1,0 = 011, division ratio = 1:8 bit 2,1,0 = 100, division ratio = 1:16 bit 2,1,0 = 101, division ratio = 1:32 bit 2,1,0 = 110, division ratio = 1:64 bit 2,1,0 = 111, division ratio = 1:128 3 wdts3 bit3=1, usbpdp, and usbpdn connected to 510k pull-high resistor bit3=0, no pull-high - default at mcu reset 4~6 not used 7 must be set 1 wdts register suspend wake-up and remote wake-up if there is no signal on the usb bus for over 3ms, the de - vice will go into a suspend mode. the suspend line (bit 0 of the usc register) will be set to 1 and a usb inter - rupt is triggered to indicate that the devices should jump to the suspend state to meet the 500 a usb suspend current spec. in order to meet the 500 a suspend current, the firm- ware should disable the usb clock by clearing the usbcken bit which is bit3 of the scc register to 0 . the suspend current is 400 a. the user can further decrease the suspend current to 250 a by setting the bgoff bit which is bit4 of the scc register. if in the usb mode set this bit lvr opt must disable. when the resume signal is sent out by the host, the de - vices will wake up the mcu with a usb interrupt and the resume line (bit 3 of the usc register) is set. in order to make the device function properly, the firmware must set the usbcken (bit 3 of the scc register) to 1 and clear the bgoff (bit4 of the scc register). since the resume signal will be cleared before the idle signal is sent out by the host, the suspend line (bit 0 of the usc register) will be set to 0 . so when the mcu is detecting the suspend line (bit0 of usc register), the resume line condition should be noted and taken into consideration. after finishing the resume signal, the suspend line will go inactive and a usb interrupt will be triggered. the fol - lowing is the timing diagram. as the device has a remote wake up function it can wake-up the usb host by sending a wake-up pulse through rmwk (bit 1 of the usc register). once the usb host receives a wake-up signal from the devices, it will send a resume signal to the device. the timing is as follows: : 7 . ! . h 7 : 7 . ! . h 7 9 ! < $ . ( 9 ! < % < 5
HT82B60R rev. 1.10 31 february 1, 2011 configure a ps2 device the devices can also be configured as a usb interface or ps2 interface device, by configuring mode_ctrl 0~1 (bit 4~5 of the usr register). if mode_ctrl 0=1, and mode_ctrl 1=0, the device will be configured as a ps2 interface, pin usbpdn is configured as a ps2 data pin and usbpdp is configured as a ps2 clk pin. the user can read or write to the ps2 data or ps2 clk pin by accessing the corresponding bit ps2_dai (bit 4 of the usc register), ps2_cki (bit 5 of the usc register), ps2_dao (bit 6 of the usc register) and sp2_cko (bit 7 of the usc register) respectively. the user should make sure that in order to read the data properly, the corresponding output bit must be set to 1 . for example, if it is desired to read the ps2 data by reading ps2_dai, then ps2_dao should set to 1 . otherwise it is always read as 0 . if mode_ctrl 0=0, and mode_ctrl 1=1, the device is configured as a usb interface. both the usbpdn and usbpdp is driven by the sie of the HT82B60R. the user can only write or read the usb data through the corresponding fifo. both the mode_ctrl 0~1 de - fault is 0 . usb interface the device includes a usb interface function permitting simplified implementation of usb type products. as the full scope of the usb specification is beyond the reach of this document, users are request to consult external documentation for further details. usb registers there are several registers used for the usb function. the awr register contains the current address and a remote wake up function control bit. the initial value of awr is 00h . the address value extracted from the usb command is not to be loaded into this register until the setup stage is completed. bit no. label r/w function 0 wken w remote wake-up enable/disable 7~1 ad6~ad0 w usb device address awr (42h) register bit no. label r/w function 0 suspend r read only, usb suspend indication. when this bit is set to 1 (set by the sie ), it indi- cates that the usb bus has entered the suspend mode. the usb interrupt is also triggered on any change of this bit. 1 rmot_ wk w usb remote wake up command. set by the mcu to force the usb host to leave the suspend mode. when this bit is set to 1 ,a2 s delay for clearing this bit to 0 is needed to insure the rmwk command is accepted by sie. 2 urst_ flag r/w usb reset indication. this bit is set/cleared by the usb sie. this bit is used to detect which bus (ps2 or usb) is attached. when the urst is set to 1 , this indicates that a usb reset has occurred (the attached bus is usb) and a usb interrupt will be in - itialised. 3 resume_o r usb resume indication. when the usb leaves the suspend mode, this bit is set to 1 (set by the sie). this bit will appear for 20ms waiting for the mcu to detect. when the resume is set by the sie, an interrupt will be generated to wake-up the mcu. in order to detect the suspend state, the mcu should set the usbcken and clear susp2 (in the scc register) to enable the sie detect function. the resume will be cleared while susp is going to 0 . when the mcu is detecting the susp, the condition of resume (which wakes-up the mcu ) should be noted and taken into consideration. 4 ps2_dai r read only, usbpdn/data input 5 ps2_cki r read only, usbpdp/clk input 6 ps2_dao w data for driving the usbpdn/data pin when working under 3d ps2 mouse func - tion. (default= 1 ) 7 ps2_cko w data for driving the usbpdp/clk pin when working under 3d ps2 mouse function. (default= 1 ) usc (20h) register
HT82B60R rev. 1.10 32 february 1, 2011 the usr (usb endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select the serial bus, ps2 or usb. the endpoint request flags, ep0if, ep1if, ep2if and ep3if, are used to indicate which endpoints are accessed. if an endpoint is accessed, the related endpoint request flag will be set to 1 and the usb in - terrupt will occur, if the usb interrupt is enabled and the stack is not full. when the active endpoint request flag is served, the endpoint request flag has to be cleared to 0 . bit no. label r/w function 0 ep0_int r/w when this bit is set to 1 (set by the sie), it indicates that endpoint 0 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 1 ep1_int r/w when this bit is set to 1 (set by the sie), it indicates that endpoint 1 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 2 ep2_int r/w when this bit is set to 1 (set by the sie), it indicates that endpoint 2 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 3 ep3_int r/w when this bit is set to 1 (set by the sie), it indicates that endpoint 3 is accessed and a usb interrupt will occur. when the interrupt has been served, this bit should be cleared by firmware. 4 5 mode_ctrl0 mode_ctrl1 r/w 00 : non-usb mode, turn-off v33o, both usbpdp and usbpdn can be read and write - default 01 : non-usb mode, has 200 between vdd and v33o, both usbpdp and usbpdn can be read and write 10 : usb mode, 1.5k between usbpdn and v33o, v33o output 3.3v, both usbpdp and usbpdn are read only 11 : non-usb mode, v33o output 3.3v, both usbpdp and usbpdn can be read and write 6 reserved 7 usb _flag r/w this flag is used to indicate that the mcu is in the usb mode - bit=1 this bit is r/w by fw and will be cleared to 0 after power-on reset - default= 0 usr (21h) register there is a system clock control register implemented to select the clock used in the mcu. this register consists of the usb clock control bit, usbcken, and a system clock selection bit, sysclk. the ps2 mode indicate bit, ps2_flag, and a system clock adjust control bit, clk_adj. bit no. label r/w function 0 reserved bit - read as 0 1 reserved bit - read as 0 2 d_sr r/w when set to 1 , a 7.5k resistor will be connected between vdd and usbpdn, and the 1.5k between usbpdn and v33o will be removed, default value is 0 . 3 usbcken r/w usb clock control bit. when this bit is set to 1 , it indicates that the usb clock is en - abled. otherwise, the usb clock is turned-off (default 0 ). 4 bgoff r/w when set to 1 , the band-gap circuit will be switched off. default value is 0 . 5 ps2_flag r/w this flag is used to indicate that the mcu is in the ps2 mode (bit=1). this bit is r/w by fw and will be cleared to 0 after power-on reset (default 0 ). 6 sysclk r/w this bit is used to specify the system oscillator frequency used by the mcu. if an inte - grated 6mhz oscillator is used, this bit should be set to 1 . if an integrated 12mhz os - cillator is used, this bit should be cleared to 0 (default). 7 clk_adj r/w this bit is used to adjust the system clock for the usb mode for temperature changes. in the power-down mode this bit should be set high to reduce power consumption. 0: enable (default) 1: disable scc (22h) register
HT82B60R rev. 1.10 33 february 1, 2011 stall and pipe, pipe_ctrl, endpt_en registers the pipe register represents whether the corresponding endpoint is accessed by the host or not. after an act_en sig - nal has been sent out, the mcu can check which endpoint had been accessed. this register is set only after the a time when the host is accessing the corresponding endpoint. the stall register shows whether the corresponding endpoint works or not. as soon as the endpoint works improp - erly, the corresponding bit must be set. the pipe_ctrl register is used for configuring the in (bit=1) or out (bit=0) pipe. the default is define in pipe. bit0 (data0) of the pipe_ctrl register is used to set the data toggle of any endpoint (except endpoint 0) using data tog - gles to the value data0. once the user wants any endpoint (except endpoint 0) using data toggles to the value data0. the user can output a low pulse to this bit. the low pulse period must at least 10 instruction cycles. the endpt_en register is used to enable or disable the corresponding endpoint (except endpoint 0) enable endpoint (bit=1) or disable endpoint (bit=0) the bitmaps are list are shown in the following table: register name r/w register address bit7~bit4 reserved bit 3 bit 2 bit 1 bit 0 default value endpt_en r/w 47h pipe 3 pipe 2 pipe 1 pipe 0 00001111 pipe_ctrl r/w 41h pipe 3 pipe 2 pipe 1 data0 00001110 stall r/w 43h pipe 3 pipe 2 pipe 1 pipe 0 00001110 pipe r 44h pipe 3 pipe 2 pipe 1 pipe 0 00000000 pipe_ctrl (41h), stall (43h), pipe (44h) and endpt_en (47h) registers the usb_stat register (40h) is used to indicate the present usb signal state. bit no. function read/write register address 0 eop r/w 01000000b 1 j_state r/w 2 k_state r/w 3 se0 r/w 4 se1 r/w 5~7 usb_stat (40h) register table func. name r/w description eop r/w this bit is used to indicate the sie has detected a eop usb signal in the usb bus. this bit is set by sie and cleared by f/w. j_state r/w this bit is used to indicate the sie has detected a j_state usb signal in the usb bus. this bit is set by sie and cleared by f/w. k_state r/w this bit is used to indicate the sie has detected a k_state usb signal in the usb bus. this bit is set by sie and cleared by f/w. unused bit, read as 0 se0 r/w this bit is used to indicate the sie has detected a se0 noise in the usb bus. this bit is set by sie and cleared by f/w. se1 r/w this bit is used to indicate the sie has detected a se1 noise in the usb bus. this bit is set by sie and cleared by f/w. usb_stat function table
HT82B60R rev. 1.10 34 february 1, 2011 the sies register is used to indicate the present signal state in which the sie receives and also defines whether the sie has to change the device address automatically. bit no. function read/write register address 0 adr_set r/w 01000001b 1 f0_err r/w 2~6 7 nmi r/w sies (45h) register table func. name r/w description adr_set r/w this bit is used to configure the sie to automatically change the device address with the value of the address+remote_wakeup register. when this bit is set to 1 by f/w, the sie will update the device address with the value of the address+remote_wakeup register after the pc host has successfully read the data from the device by the in operation. the sie will clear the bit after updating the device address. otherwise, when this bit is cleared to 0 , the sie will update the device address immediately after an address is written to the address+remote_wakeup register. default 0. f0_err r/w this bit is used to indicate that some errors have occurred when accessing the fifo0. this bit is set by sie and cleared by f/w. default 0 unused bit, read as 0 nmi r/w this bit is used to control whether the usb interrupt is output to the mcu in a nak response to the pc host in or out token. only for endpoint0 1: has only usb interrupt, data is transmitted to the pc host or data is received from the pc host 0: always has usb interrupt if the usb accesses fifo0 default 0 sies function table
HT82B60R rev. 1.10 35 february 1, 2011 the misc register combines a command and status to control desired endpoint fifo action and to show the status of the desired endpoint fifo. the misc will be cleared by the usb reset signal. bit no. label r/w function 0 req r/w after setting the other status of the desired one in the misc, endpoint fifo can be requested by setting this bit to 1 . after the task is completed, this bit must be cleared to 0 . 1 tx r/w this bit defines the direction of data transferring between the mcu and endpoint fifo. when the tx is set to 1 , this means that the mcu wants to write data to the endpoint fifo. after the task is completed, this bit must be cleared to 0 before ter - minating the request to represent the end of transferring. for a read action, this bit has to be cleared to 0 to represent that mcu wants to read data from the endpoint fifo and has to be set to 1 after completion. 2 clear r/w clear the requested endpoint fifo, even if the endpoint fifo is not ready. 4 3 selp1 selp0 r/w defines which endpoint fifo is selected, selp1,selp0: 00: endpoint fifo0 01: endpoint fifo1 10: endpoint fifo2 11: endpoint fifo3 5 scmd r/w used to show that the data in the endpoint fifo is a setup command. this bit has to be cleared by firmware. that is to say, even if the mcu is busy, the device will not miss any setup commands from the host. 6 ready r read only status bit, this bit is used to indicate that the desired endpoint fifo is ready for operation. 7 len0 r/w used to indicate that a 0-sized packet has been sent from a host to the mcu. this bit should be cleared by firmware. misc (46h) register the mcu can communicate with the endpoint fifo by setting the corresponding registers, of which the address is listed in the following table. after reading the current data, the next data will show after 2 s, this is used to check the endpoint fifo status and response to the misc register, if the read/write action is still going on. registers r/w address bit7~bit0 fifo0 r/w 48h data7~data0 fifo1 r/w 49h data7~data0 fifo2 r/w 4ah data7~data0 fifo3 r/w 4bh data7~data0 there are some timing constrains and usages illustrated here. by setting the misc register, the mcu can perform read - ing, writing and clearing actions. there are some examples shown in the following table for endpoint fifo reading, writ - ing and clearing. actions misc setting flow and status read fifo0 sequence 00h 01h delay 2 s, check 41h read* from fifo0 register and check not ready (01h) 03h 02h write fifo0 sequence 02h 03h delay 2 s, check 43h write* to fifo0 register and check not ready (03h) 01h 00h check whether fifo0 can be read or not 00h 01h delay 2 s, check 41h (ready) or 01h (not ready) 00h check whether fifo0 can be written or not 02h 03h delay 2 s, check 43h (ready) or 03h (not ready) 02h write 0-sized packet sequence to fifo0 02h 03h delay 2 s, check 43h 01h 00h clear fifo1 sequence 01h delay 2s 05h delay 2s 00h note: *: there is a 2 s time between 2 read actions or between 2 write actions.
HT82B60R rev. 1.10 36 february 1, 2011 register bits read/write functions tbhp 0~4 r store current table read bit12~bit8 data tbhp register lcd driver the devices have the capability of driving external lcd panels. the common pins for lcd driving, com0~ com3, are pin shared with certain pin on the pc port. lcd driver operation an external lcd panel can be driven using by configur - ing certain pins on the pc as common pins and using other output lines as segment pins. the lcd driver function is controlled using the lcdc register which in addition to controlling the overall on/off function also controls the bias voltage setup function. this enables the lcd driver to generate the necessary vdd/2 volt - age levels for lcd 1/2 bias operation. the register bits, control the overall on/off and bias cur - rent selection as well as selecting which pc pins are to be used as lcd common drivers. the lcden bit in the lcdc register is the overall mas - ter control for the lcd driver, however this bit is used in conjunction with the comnen bits to select which port c pins are used for lcd driving. note that the port con - trol register does not need to first setup the pins as out - puts to enable the lcd driver operation. lcden comnen pcc pin function o/p level 0 x x i/o 0or1 1 0 x i/o 0or1 1 1 x com v dd /2 com pin output control lcd bias control the lcd com driver enables a range of selections to be provided to suit the requirement of the lcd panel which is being used. the bias resistor choice is imple- mented using the rsel0 and rsel1 bits in the lcdc register. * 2 m / ( : 7 ! : 7 ( : 7 lcd com bias b i t76543210 name rsel1 rsel0 lcden com3en com2en com1en com0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 00000000 lcd register
HT82B60R rev. 1.10 37 february 1, 2011 serial interface function the device contains a serial interface function, which includes both the four line spi interface and the two line i 2 c interface types, to allow an easy method of commu- nication with external peripheral hardware. having rela- tively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins therefore the sim in- terface function must first be selected using a configura - tion option. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using a bit in an internal register. spi interface the spi interface is often used to communicate with ex - ternal peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple commu - nication protocol simplifying the programming require - ments when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the mcu can be either master or slave. although the spi interface specification can control multiple slave devices from a single master, here, as only a single select pin, scs , is provided only one slave device can be connected to the spi bus. spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface must first be enabled by selecting the sim enable con - figuration option and setting the correct bits in the simctl0/simctl2 register. after the spi configura - tion option has been configured it can also be addi - tionally disabled or enabled using the simen bit in the simctl0 register. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations be - ing implemented by the master. the master also con - trols the clock signal. as the device only contains a single scs pin only one slave device can be utilised. +
) ! +
' , 9 9 spi master/slave connection * - *
! 2 2 $ c 2 2 c 2 $ $ $ c $ 2 c $ % % $ c % 2 c % / / $ c / 2 c / ( ! 1 1 ! $ c ! 2 c . 0 . $ c ! " " ! 7 2 c 0 ' 1 " ! 7 c ! 2 2 : 7 4 : ( 2 $ : 7 % : 7 / : 7 ( : 7 : ( $ % ? $ 2 2 a % ? 5 2 a % ? % 5 a % ? $ % < 5 a : ( $ 2 2 $ $ : ( 2 2 $ 2 $ . 8 5 * % 5 8 5 2 8 $ 2 2 8 % 2 2 8 lcdc register
HT82B60R rev. 1.10 38 february 1, 2011 the spi function in this device offers the following fea - tures: full duplex synchronous data transfer both master and slave modes lsb first or msb first data transmission modes transmission complete flag rising or falling active clock edge wcol and csen bit enabled or disable select the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of cer - tain control bits such as csen, simen and scs . there are several configuration options associated with the spi interface. one of these is to enable the sim function which selects the sim pins rather than normal i/o pins. note that if the configuration option does not select the sim function then the simen bit in the simctl0 register will have no effect. another two sim configuration options determine if the csen and wcol bits are to be used. configuration option function sim function sim interface or i/o pins spi csen bit enable/disable spi wcol bit enable/disable spi interface configuration options spi registers there are three internal registers which control the over - all operation of the spi interface. these are the simdr data register and two control registers simctl0 and simctl2. note that the simctl1 register is only used by the i 2 c interface. configuration option register i/o status note simctl0 simctl2 sim function spi_csen simen csen spi scs 0 x x x i/o i/o 1 x 0 x i/o i/o 1 0 1 x spi i/o scs not floating 1 1 1 0 spi i/o scs not floating 1 1 1 1 spi scs . ! ! ? ? 1 .
! 1 ! " ! + + : ! ( + a :
! a 1 b 9 ! ! ! 1 ! " ! : 7 : ! 9 : - 9 ( spi block diagram
HT82B60R rev. 1.10 39 february 1, 2011 the simdr register is used to store the data being trans - mitted and received. the same register is used by both the spi and i 2 c functions. before the microcontroller writes data to the spi bus, the actual data to be transmit - ted must be placed in the simdr register. after the data is received from the spi bus, the microcontroller can read it from the simdr register. any transmission or reception of data from the spi bus must be made via the simdr register. bit76543210 label sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por xxxxxxxx there are also two control registers for the spi inter - face, simctl0 and simctl2. note that the simctl2 register also has the name simar which is used by the i 2 c function. the simctl1 register is not used by the spi function, only by the i 2 c function. register simctl0 is used to control the enable/disable function and to set the data transmission clock frequency. although not connected with the spi function, the simctl0 register is also used to control the peripheral clock prescaler. register simctl2 is used for other control functions such as lsb/msb selection, write collision flag etc. the following gives further explanation of each simctl0 register bit: simen the bit is the overall on/off control for the spi inter- face. when the simen bit is cleared to zero to disable the spi interface, the sdi, sdo, sck and scs lines will be in a i/o mode and the spi operating current will be reduced to a minimum value. when the bit is high the spi interface is enabled. the sim configuration option must have first enabled the sim interface for this bit to be effective. note that when the simen bit changes from low to high the contents of the spi con - trol registers will be in an unknown condition and should therefore be first initialised by the application program. sim0~sim2 these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 corspi function, they are used to control the spi mas - ter/slave selection and the spi master clock fre - quency. if the spi slave mode is selected then the clock will be supplied by an external master device. sim0 sim1 sim2 spi master/slave clock control and i2c enable 0 0 0 spi master, f sys /4 0 0 1 spi master, f sys /16 0 1 0 spi master, f sys /64 0 1 1 spi master, f sys 1 0 0 spi master, f sys /2 1 0 1 spi slave 110i 2 c mode 1 1 0 not used spi control register simctl2 the simctl2 register is also used by the i 2 c interface but has the name simar . trf the trf bit is the transmit/receive complete flag and is set high automatically when an spi data transmis - sion is completed, but must be cleared by the applica - tion program. it can be used to generate an interrupt. wcol the wcol bit is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simdr register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the wcol bit can be disabled or enabled via configu- ration option. csen the csen bit is used as an on/off control for the scs pin. if this bit is low then the scs pin will be disabled and placed into i/o mode. if the bit is high the scs pin will be enabled and used as a select pin. note that us - ing the csen bit can be disabled or enabled via con - figuration option. mls this is the data shift select bit and is used to select how the data is transferred, either msb or lsb first. setting the bit high will select msb first and low for lsb first. ckeg and ckpol these two bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be configured before data trans - fer is executed otherwise an erroneous clock edge
HT82B60R rev. 1.10 40 february 1, 2011 may be generated. the ckpol bit determines the base condition of the clock line, if the bit is high then the sck line will be low when the clock is inactive. when the ckpol bit is low then the sck line will be high when the clock is inactive. the ckeg bit deter - mines active clock edge type which depends upon the condition of ckpol . ckpol ckeg sck clock signal 00 high base level active rising edge 01 high base level active falling edge 10 low base level active falling edge 11 low base level active rising edge spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simdr register, transmission/reception will begin si - multaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simdr register will be transmitted and any data on the sdi pin will be shifted into the simdr regis- ter. the master should output an scs signal to enable the slave device before a clock signal is provided and slave data transfers should be enabled/disabled be- fore/after an scs signal is received. the spi will continue to function even after a halt in- struction has been executed. i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data trans - fer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this rea - son it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identified by a unique address which will be transmitted and re - ceived on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. there are several configuration options associated with the i 2 c interface. one of these is to enable the function which selects the sim pins rather than normal i/o pins. note that if the configuration option does not select the sim function then the simen bit in the simctl0 register will have no effect. a configuration option exists to allow a clock other than the system clock to drive the i 2 c interface. another configuration option determines the debounce time of the i 2 c inter- face. this uses the internal clock to in effect add a debounce time to the external clock to reduce the pos- sibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 1 or 2 system clocks. sim function sim function sim interface enable or disable i 2 c debounce no debounce, 1 system clock; 2 system clocks i 2 c interface configuration options i 2 c registers there are three control registers associated with the i 2 c bus, simctl0, simctl1 and simar and one data register, simdr . the simdr register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simdr register. after the data is received from the i 2 c bus, the microcontroller can read it from the simdr register. any transmission or reception of data from the i 2 c bus must be made via the simdr register. 8 ! 1 ! 0 ! 1 8 a ! ) 1 0 !
1 8 a ! ) 1 0 ! 1
HT82B60R rev. 1.10 41 february 1, 2011 + ) *
! 7 " ! d n 2 g % ! 1 ! $ c ! 2 c " a ! ) % 0 ! a ! % $ 2 2 : 7 d 1 b 6 d 1 b $ # d 1 b # 6 d 1 b d 1 b % 0 % 7 2 2 2 2 $ $ $ $ 2 2 $ $ 2 2 $ $ 4 $ 2 % 2 $ 2 $ 2 $ 2 $ 9 : 7 9 $ 9 2 spi/i 2 c control register simctl0 + ) *
! 4 ! 0 " 1 $ c 1 ! 2 c ! " ! 1 $ c ! 2 c ! ! " ! ! $ c ! 2 c 1 ! 1 $ c . 2 c ( . a : $ c ? 2 c ? a
$ c ? 2 c ? 7 " ! d g 2 g 2 ( + : 7 ( 9 : - 9 ( spi control register simctl2 + ) *
! 4 0 a ! ) 1 $ c ! a ! ) 2 c a ! ) 7 " ! d g 2 g ) , 1 $ c , 2 c , ) ! a ! ) 1 $ c ! n a ! ) 2 c a ! ) ! 0 $ c ! 2 c 0 %
1 $ c
2 c !
! 1 $ c 2 c ! ! 1 1 $ c ! 1 " 2 c ! 1 ! " 2 & ; ; 8 9 ; 8 9 & . . & 8 8 & + i 2 c control register simctl1
HT82B60R rev. 1.10 42 february 1, 2011 9 = 9 ( k $ > 9 = 9 ( k 2 > " 4 2 # $ 5 % 6 / / 6 % 5 $ # 2 4 = ! ! ! 1 9 > spi slave mode timing (ckeg=0) 9 = 9 ( k $ d 9 : - k 2 > : 7 d : 7 k $ : 7 k $ d : 7 k 2 = > 9 = 9 ( k 2 d 9 : - k 2 > 9 = 9 ( k $ d 9 : - k $ > 9 = 9 ( k 2 d 9 : - k $ > = 9 : - k 2 > = 9 : - k $ > " 4 2 # $ 5 % 6 / / 6 % 5 $ # 2 4 4 2 # $ 5 % 6 / / 6 % 5 $ # 2 4 spi master mode timing 9 = 9 ( k $ > 9 = 9 ( k 2 > " 4 2 # $ 5 % 6 / / 6 % 5 $ # 2 4 = ! ! ) ! l k 1 ! 1 k $ > 7 c + 0 d 1 : 7 k $ ! : 7 k 2 d )
! ! ! 0 < spi slave mode timing (ckeg=1)
HT82B60R rev. 1.10 43 february 1, 2011 : 7 k $ ! ( k $ o ( b ! ! " o = + k $ o > 7 b 1 + ! 1 + ! o 7 b : 7 0 0 8 8 ! 1 ! 1 : 7 ! ( e % c 2 f k 2 2 2 d 2 2 $ d 2 $ 2 d 2 $ $ $ 2 2 e % c 2 f k $ 2 $ 7 spi transfer control flowchart % = > 0 8 = 8 > 1 ! ! ; 8 & 8 8 . % ! " ! ( . . ! 0 ! ! " " . 8 " : ! 8 a ! ) ) 0 . & . . . & ; . ( ! 8 ! & + . i 2 c block diagram
HT82B60R rev. 1.10 44 february 1, 2011 simen the simen bit is the overall on/off control for the i 2 c interface. when the simen bit is cleared to zero to disable the i 2 c interface, the sda and scl lines will be in a i/o mode and the i 2 c operating current will be reduced to a minimum value. in this condition the pins can be used as seg functions. when the bit is high the i 2 c interface is enabled. the sim configura - tion option must have first enabled the sim interface for this bit to be effective. note that when the simen bit changes from low to high the contents of the i 2 c control registers will be in an unknown condition and should therefore be first initialised by the appli - cation program sim0~sim2 these bits setup the overall operating mode of the sim function. to select the i 2 c function, bits sim2~ sim0 should be set to the value 110. rxak the rxak flag is the receive acknowledge flag. when the rxak bit has been reset to zero it means that a correct acknowledge signal has been re - ceived at the 9th clock, after 8 bits of data have been transmitted. when in the transmit mode, the transmitter checks the rxak bit to determine if the receiver wishes to receive the next byte. the trans - mitter will therefore continue sending out data until the rxak bit is set high. when this occurs, the transmitter will release the sda line to allow the master to send a stop signal to release the bus. srw the srw bit is the slave read/write bit. this bit de- termines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address match, that is when the haas bit is set high, the device will check the srw bit to determine whether it should be in transmit mode or receive mode. if the srw bit is high, the master is requesting to read data from the bus, so the device should be in transmit mode. when the srw bit is zero, the master will write data to the bus, therefore the device should be in receive mode to read this data. txak the txak flag is the transmit acknowledge flag. af - ter the receipt of 8-bits of data, this bit will be trans - mitted to the bus on the 9th clock. to continue receiving more data, this bit has to be reset to zero before further data is received. htx the htx flag is the transmit/receive mode bit. this flag should be set high to set the transmit mode and low for the receive mode. hbb the hbb flag is the i 2 c busy flag. this flag will be high when the i 2 c bus is busy which will occur when a start signal is detected. the flag will be reset to zero when the bus is free which will occur when a stop signal is detected. hass the hass flag is the address match flag. this flag is used to determine if the slave device address is the same as the master transmit address. if the ad - dresses match then this bit will be high, if there is no match then the flag will be low. hcf the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon com - pletion of an 8-bit data transfer the flag will go high and an interrupt will be generated. i 2 c control register simar the simar register is also used by the spi interface but has the name simctl2. the simar register is the location where the 7-bit slave address of the microcontroller is stored. bits 1~7 of the simar register define the microcontroller slave ad - dress. bit 0 is not defined. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the simar register, the microcontroller slave device will be selected. i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmis - sion, a data transmission and finally a stop signal. when a start signal is placed on the i 2 c bus, all de- vices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. the first seven bits of the data will be the slave address with the first bit being the msb. if the address of the microcontroller matches that of the transmitted address, the haas bit in the simctl1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service rou- tine, the microcontroller slave device must first check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the microcontroller to de - termine whether to go into transmit or receive mode. be - fore any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: step 1 write the slave address of the microcontroller to the i 2 c bus address register simar. step 2 set the simen bit in the simctl0 register to 1 to en - able the i 2 c bus.
HT82B60R rev. 1.10 45 february 1, 2011 step 3 set the esim bit of the interrupt control register to en - able the i 2 c bus interrupt. start signal the start signal can only be generated by the mas - ter device connected to the i 2 c bus and not by the microcontroller , which is only a slave device. this start signal will be detected by all devices con - nected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to deter- mine which slave device the master wishes to com- municate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, de - fines the read/write status and will be saved to the srw bit of the simctl1 register. the device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the microcontroller slave device will also set the status flag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the in - terrupt source has come from a matching slave ad - dress or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simdr register, or in the receive mode where it must implement a dummy read from the simdr regis - ter to release the scl line. srw bit the srw bit in the simctl1 register defines whether the microcontroller slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the microcontroller should examine this bit to determine if it is to be a transmitter or a receiver. if the srw bit is set to 1 then this indicates that the master wishes to read data from the i 2 c bus, therefore the microcontroller slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw bit is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the microcontroller slave device must be setup to read data from the i 2 c bus as a receiver. acknowledge bit after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. this acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas bit is high, the addresses have matched and the microcontroller slave device must check the srw bit to determine if it is to be a transmitter or a receiver. if the srw bit is high, the microcontroller slave device should be setup to be a transmitter so the htx bit in the simctl1 register should be set to 1 if the srw bit is low then the microcontroller slave device should be setup as a receiver and the htx bit in the simctl1 register should be set to 0 . + )
! 4 7 " ! d g 2 g % 0 0 2 8 5 8 6 8 # 8 2 8 / 8 % 8 $ i 2 c slave address register simar 0 8 8 : e % c 2 f k $ $ 2 : : 7 % . ! " k o : ! : : & 1 ! " - ! ( : & & + ) ! % . - ! i 2 c bus initialisation flow chart
HT82B60R rev. 1.10 46 february 1, 2011 & 8 8 k $ o & ; k $ o k $ o b 7 b 7 ; 8 9 k $ o b 7 7 1 : b
1 : : : & ;
+ ( & ; ( ; 8 9 : : ( & ; ( ; 8 9 i 2 c bus isr flow chart $ 2 $ 2 2 $ 22 $ 2 2 $ 2 $ 2 $ $ k = $ > 8 k 0 8 = 4 > k = $ > k 0 0 ! a ! ) = $ > k = > 8 k 8 9 = ; 8 9 1 ! d ; 8 9 1 0 $ > k " = $ > ( 8 8 9 8 9 " ( 8 0 8 8 8 8 8 8 8 i 2 c communication timing diagram
HT82B60R rev. 1.10 47 february 1, 2011 data byte the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb first and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge sig - nal, level 0 , before it can receive the next data byte. if the transmitter does not receive an acknowledge bit signal from the receiver, then it will release the sda line and the master will send out a stop signal to re - lease control of the i 2 c bus. the corresponding data will be stored in the simdr register. if setup as a transmitter, the microcontroller slave device must first write the data to be transmitted into the simdr regis - ter. if setup as a receiver, the microcontroller slave de - vice must read the transmitted data from the simdr register. receive acknowledge bit when the receiver wishes to continue to receive the next data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the microcontroller slave device, which is setup as a transmitter will check the rxak bit in the simctl1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen via pcken in the simctl0 register. the clock source for the pe - ripheral clock output originates from the system clock or a divided ration of the system clock. the pcken bit in the simctrl0 register is the overall on/off control, set - ting pcken bit high enables the peripheral clock, clear - ing the bit to zero disables it. the required division ratio of the system clock is selected using the pckp1 and pckp0 bits in the same register. if the device is pow - ered down, this will disable the peripheral clock output. ( 8 ) ! " data timing diagram 1 b : 0 ! ! 2 % ( 9 : - ( 9 : - $ d 6 d 9 : 7 9 2 9 $ " peripheral clock block diagram + ) *
! 7 " ! d n 2 g % ! 1 ! $ c ! 2 c 9 " a " " a ! $ c a ! " ! 2 c a ! " 0 ! a ! ) 2 a 1 b 1 b 6 1 b 1 b % 9 $ 2 2 $ $ 9 2 2 $ 2 $ : 7 4 $ 2 % 9 : 7 9 $ 9 2 peripheral clock output control simctl0
application circuits note: the resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res high. components with * are used for emc issue. HT82B60R rev. 1.10 48 february 1, 2011 . ( 9 . 7 8 8 * / / * . . @ * 2 < $ + * : * 2 < $ + $ 2 2 a $ 2 + 2 < $ + 8 2 m 8 4 . 2 m . 4 2 m 4 2 m 4 : 2 m : 4 $ 2 a + 2 m + $
HT82B60R rev. 1.10 49 february 1, 2011 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
HT82B60R rev. 1.10 50 february 1, 2011 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
HT82B60R rev. 1.10 51 february 1, 2011 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] (4) tabrdc [m] (5) tabrdl [m] read rom code (locate by tblp and tbhp) to data memory and tblh read rom code (current page) to data memory and tblh read table (last page) to tblh and data memory 2 note 2 note 2 note none none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. 4. configuration option tbhp option is enabled 5. configuration option tbhp option is disabled
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z HT82B60R rev. 1.10 52 february 1, 2011
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf HT82B60R rev. 1.10 53 february 1, 2011
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf HT82B60R rev. 1.10 54 february 1, 2011
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z HT82B60R rev. 1.10 55 february 1, 2011
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none HT82B60R rev. 1.10 56 february 1, 2011
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c HT82B60R rev. 1.10 57 february 1, 2011
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none HT82B60R rev. 1.10 58 february 1, 2011
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c HT82B60R rev. 1.10 59 february 1, 2011
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none HT82B60R rev. 1.10 60 february 1, 2011
tabrdc [m] move the rom code (locate by tblp and tbhp) to tblh and data memory (rom code tbhp is enabled) description the low byte of rom code addressed by the table pointers (tblp and tbhp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op- eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z HT82B60R rev. 1.10 61 february 1, 2011
package information 20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.158 c 0.008 0.012 c 0.335 0.347 d 0.049 0.065 e 0.025 f 0.004 0.010 g 0.015 0.050 h 0.007 0.010 08 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 4.01 c 0.20 0.30 c 8.51 8.81 d 1.24 1.65 e 0.64 f 0.10 0.25 g 0.38 1.27 h 0.18 0.25 08 HT82B60R rev. 1.10 62 february 1, 2011 % 2 $ $ $ $ 2 8 . : + n - &
28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.008 0.012 c 0.386 0.394 d 0.054 0.060 e 0.025 f 0.004 0.010 g 0.022 0.028 h 0.007 0.010 08 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.20 0.30 c 9.80 10.01 d 1.37 1.52 e 0.64 f 0.10 0.25 g 0.56 0.71 h 0.18 0.25 08 HT82B60R rev. 1.10 63 february 1, 2011 % $ $ 5 $ 6 8 . + n - & :
48-pin ssop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.395 0.420 b 0.291 0.299 c 0.008 0.012 c 0.613 0.637 d 0.085 0.099 e 0.025 f 0.004 0.010 g 0.025 0.035 h 0.004 0.012 08 symbol dimensions in mm min. nom. max. a 10.03 10.67 b 7.39 7.59 c 0.20 0.30 c 15.57 16.18 d 2.16 2.51 e 0.64 f 0.10 0.25 g 0.64 0.89 h 0.10 0.30 08 HT82B60R rev. 1.10 64 february 1, 2011 6 $ % 5 % 6 8 . + n - & :
saw type 32-pin (5mm 5mm) qfn outline dimensions symbol dimensions in inch min. nom. max. a 0.028 0.031 a1 0.000 0.002 a3 0.008 b 0.007 0.012 d 0.197 e 0.197 e 0.020 d2 0.049 0.128 e2 0.049 0.128 l 0.012 0.020 k symbol dimensions in mm min. nom. max. a 0.70 0.80 a1 0.00 0.05 a3 0.20 b 0.18 0.30 d 5.00 e 5.00 e 0.50 d2 1.25 3.25 e2 1.25 3.25 l 0.30 0.50 k HT82B60R rev. 1.10 65 february 1, 2011 : 8 $ 8 / 8 % ( : % 9 $ 3 $ # $ 4 % 6 % 5 / %
48-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.020 f 0.008 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.50 f 0.20 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 07 HT82B60R rev. 1.10 66 february 1, 2011 / # % 5 / 4 % 6 $ / $ % $ 6 8 . : + - & p 9
product tape and reel specifications reel dimensions ssop 20s (150mil), ssop 28s (150mil) symbol description dimensions in mm a reel outer diameter 330.0
1.0 b reel inner diameter 100.0
1.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0
0.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.2
0.2 ssop 48w symbol description dimensions in mm a reel outer diameter 330.0
1.0 b reel inner diameter 100.0
0.1 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.0
0.5 t1 space between flange 32.2 +0.3/-0.2 t2 reel thickness 38.2
0.2 HT82B60R rev. 1.10 67 february 1, 2011 8 . $ %
carrier tape dimensions ssop 20s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.0
0.1 e perforation position 1.75
0.10 f cavity to perforation (width direction) 7.5
0.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0
0.1 p1 cavity to perforation (length direction) 2.0
0.1 a0 cavity length 6.5
0.1 b0 cavity width 9.0
0.1 k0 cavity depth 2.3
0.1 t carrier tape thickness 0.30
0.05 c cover tape width 13.3
0.1 ssop 28s (150mil) symbol description dimensions in mm w carrier tape width 16.0
0.3 p cavity pitch 8.0
0.1 e perforation position 1.75
0.1 f cavity to perforation (width direction) 7.5
0.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0
0.1 p1 cavity to perforation (length direction) 2.0
0.1 a0 cavity length 6.5
0.1 b0 cavity width 10.3
0.1 k0 cavity depth 2.1
0.1 t carrier tape thickness 0.30
0.05 c cover tape width 13.3
0.1 HT82B60R rev. 1.10 68 february 1, 2011 $ $ 2 : + 9 2 . 2 8 2 " a " ! $ ! ! < &
ssop 48w symbol description dimensions in mm w carrier tape width 32.0
0.3 p cavity pitch 16.0
0.1 e perforation position 1.75
0.10 f cavity to perforation (width direction) 14.2
0.1 d perforation diameter 2 min. d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.0
0.1 p1 cavity to perforation (length direction) 2.0
0.1 a0 cavity length 12.0
0.1 b0 cavity width 16.2
0.1 k1 cavity depth 2.4
0.1 k2 cavity depth 3.2
0.1 t carrier tape thickness 0.35
0.05 c cover tape width 25.5
0.1 HT82B60R rev. 1.10 69 february 1, 2011 $ $ 2 : + 9 % . 2 8 2 9 $ " a " ! $ ! ! < & = > & = : " >
HT82B60R rev. 1.10 70 february 1, 2011 copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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